A new central compute platform runs safety-relevant functions and infotainment on one high-performance processor, separated by a type-1 hypervisor, with a safety microcontroller supervising it. The silicon vendors' safety manuals had to become requirements the platform teams could build and verify.
- Platform software safety requirements and architecture, handed to the implementation teams
- Hardware monitor requirements derived from the silicon vendors' safety manuals
- Health supervision and safe-state reactions between the main processor and the safety microcontroller
- Safety-relevant camera and display paths
- Software FMEA of the supervision and reaction chain